AI-Enhanced DFT Strategies and Test Implementation

Design-for-Test is what makes manufactured silicon verifiable. Every die that ships is screened by structural test, and the quality of that screen decides what reaches customers and what test costs across millions of units — which makes DFT one of the quieter but more consequential disciplines in the semiconductor industry. It is also full of slow but necessary work: requirements checklists, scan configuration and partition files, design-rule check logs, chain traceability, coverage debug, and failure log extraction. This talk shows where AI helps with each of them, from RTL design through to silicon failure analysis, and how the work changes when a tool can read volume, draft a first pass, and check its own output. The time saved is real — but the more important point is what does not change. Patterns are still simulated. Design checks still gate tape-out. AI shortens the path to an answer; engineers remain the gatekeepers of what is true.